1. Field of the Invention
The present invention relates to electronic design automation, and more particularly, to design layouts for integrated circuits.
2. Description of Related Art
A specialized field, commonly referred to as “electronic design automation” (EDA), has evolved to handle the demanding and complicated task of designing, laying out and verifying integrated circuit (IC) semiconductor chips. In EDA, computers are extensively used to automate the design, layout and verification process. The first step of the EDA design process typically involves the formal specification of the design, using hardware design languages such as Verilog or VHDL, and synthesis of the design into netlists of devices to be placed and routed. Typically, the synthesized design is stored on a computer tape or disk. The next step of the process typically involves the use of circuit simulation software to test the synthesized design of the IC to see if it operates as needed.
Once the IC design has been verified through computer simulation, the third step in the EDA design process is the use of layout software to generate component placement and interconnections for the components. However, before fabrication on the semiconductor chip begins, extensive further verification and/or testing are typically performed to further verify and check that the IC has been properly designed and physically laid out. This is accomplished in a fourth step of the EDA design process wherein design checks are performed, and IC simulation software and/or emulation system are used to test the operation and performance of the proposed IC. A pre-defined set of rules are also stored. These rules may specify certain dimensions and other criteria for checking to determine whether the new design has been properly laid out. Thereafter, simulation and/or emulation may be performed. Hence, new designs and layouts are subjected to a host of rigorous verification and testing procedures, including procedures which check the physical layout to ensure that it meets certain well-established rules or guidelines.
Often, several iterations of the design, layout, and verification process are required in order to optimize the IC's size, cost, heat output, speed, power consumption, and electrical functionalities. After the IC design has been established to be good, the fifth step in the EDA process involves the use of mask fabrication software to generate masks for manufacturing the ICs, which are then used to manufacture IC prototypes. These IC prototypes are further tested by automated test equipment (ATE).
When a semiconductor process is an n-well process (PMOS devices formed in n-wells), the NMOS devices of an integrated circuit (IC) chip share a common p-substrate. This is illustrated in FIG. 1 by a simple semiconductor wafer 10 having a p-substrate 12. In this simplified example, the wafer 10 has a pair of n-wells 14 and 16 formed in a p-epitaxy or p-epi layer 18. The p-epitaxy layer 18 is deposited epitaxially (deposition of vapors) on top of the p-substrate 12. A plurality of first PMOS devices (not shown) may be formed in the n-well 14 and a plurality of second PMOS devices (not shown) may be formed in n-well 16. A plurality of NMOS devices (not shown) may be formed in the p-epitaxy layer 18. The wafer cross-section of FIG. 1 illustrates that in the n-well process the body terminals for applying a body bias voltage (i.e., “body bias”) for PMOS devices are the n-wells 12 and 14 and the body terminal for NMOS devices is the p-epitaxy layer 18 and the p-substrate 12. Hence, the NMOS devices would have a common body terminal in the p-substrate 12, whereas the first and second PMOS devices have isolated, non-common body terminals of the n-well 12 and n-well 14, respectively. When a semiconductor process is a p-well process (NMOS devices formed in p-wells), the PMOS devices of an IC design, formed in an N-epi layer, share a common N substrate.
FIG. 2 shows the cross-section of an NMOS device 20 in an IC chip using the prior art n-well process shown in FIG. 1, with the NMOS device 20 having an n+ drain 21, a drain contact 22, an n+ gate 24, an n+ source 25, a source contact 26, and a body contact 28. The body contact 28 (also referred to as p-substrate contact, p-substrate tap or p-tap) is connected at one end to a p-epitaxy layer 30 and also through the p-epitaxy layer 30 via a highly doped p+ region 31 to a p-substrate 32. The p-epitaxy layer 30 and the p+ region 31 are physically separate but electrically the same (shorted), since they are of the same doping type (P type). The plus sign of the p+ region 31 merely indicates that the doping levels are higher in the p+ region 31. The p+ region 31 extends through the entire p-epitaxy layer 30 and abuts against the p-substrate 32 to provide an electrical path to the p-substrate 32 which circumvents the high resistance of the lightly doped p-epitaxy layer 30. The body contact 28 is connected at the other end to the source contact 26 that is at 0 volts (ground). Hence, the body contact 28 is shorted to ground. The source and body contacts 26 and 28 combine to form a U-shaped metal contact, labeled “METAL1”, with an insulating material 33 included in the interior of the U-shaped metal contact.
FIG. 3 shows a schematic diagram of the NMOS device 20 of FIG. 2 wherein the source 25 and the body (p-epitaxy layer 30 and the p-substrate 32) are shorted together; hence, a body bias voltage Vbb applied from the source 25 to the p-epitaxy layer 30 is zero. By definition, the NMOS device 20 has a zero body bias or no body bias. Depending upon the application, the NMOS device 20 may be modified to have a non-zero body bias voltage Vbb. In such a case, when the NMOS device 20 is in an active mode, the voltage Vbb is such that a forward bias is applied, which in turn increases the threshold voltage of the NMOS device 20. Likewise, a reverse bias Vbb may be applied to lower the threshold voltage. Body bias has several applications including leakage current control and adaptive frequency modulation.
In the prior art, most designs that require body bias have to be planned in advance during the EDA process, since inclusion of body bias requires the routing of an additional sparse bias grid and an on-chip bias circuit to generate the body bias voltage Vbb. If off-chip bias generation is included in the IC design, then the chip planning has to be done for the bias grids.